The present invention relates to a SDH test apparatus and a SDH test method, and particularly a SDH test apparatus for substituting a part of payload of received SDH data with a desired data and transmitting, wherein the time difference between processing for SOH portion and processing for AU portion can be absorbed by a simple configuration and a SDH test method.
Conventionally, in the STM (synchronized transfer mode) system for multiplexing a plurality of series of data in synchronization and transferring, SDH (synchronized digital hierarchy) data is used.
As it is well known, there are various standards for STM, and as for SDH data prescribed by the most basic STM-1, one frame is composed of a SOH (section overhead) portion of 9×9 bytes and a payload of 261×9 bytes, as shown in FIG. 5.
As shown in FIG. 6, as for SDH data, SOH portion and payload are transferred alternatively by 9 bytes and 261 bytes respectively.
Here, information is inserted into the payload of SDH data taking a position A (this position is a position later in time than the AU pointer AUP insertion position) indicated by the value of AU (administrative unit) pointer AUP inserted at the fourth byte of SOH portion as leading head position.
Before testing the operation of systems or the like for data communication using this SDH data, sometimes it is desired to test by substituting a part of payload of SDH data to be transferred with a desired data (for instance, pseudo random signal).
In order to insert a desired data into a part of payload of SDH data and output in this way, it is necessary to proceed as follows.
First, SOH portion and payload are extracted from the input SDH data, and a desired data is inserted into a desired position of the payload for generating data for transmission.
Next, SDH data frame is generated based on this generated data and SOH data extracted from the reception data and output.
However, when a new data is generated by rewriting a part of payload, as it takes longer time than the processing time of SOH data, it is inconvenient to generate a frame data by simply combining SOH portion of received SDH data and data of newly generated payload section.
In other words, that is, if, frame data is generated by a simple combination as mentioned above, information lead head position is shifted by the difference of payload processing time and SOH data processing time.
In order to solve this problem, in the prior art, the processing of SOH data is delayed according to data processing time of the payload.
FIG. 7 shows a configuration of a SDH test apparatus 10 of the prior art for generating SDH data by delaying the processing for SOH data.
This SDH test apparatus 10 comprises a reception SOH processing portion (Rx SOH processor) 11 for performing various processing including frame detection of received SDH data, channel selection, detection of data inserted into the SOH portion, error check or others, a reception AU processing portion (Rx AU processor) 12, a transmission AU processing portion (Tx AU processor) 13 for generating AU data by substituting data of a predetermined position of the payload of data extracted by the Rx AU processor 12 with a desired data, a delay processing portion 14 for delaying SOH data processed by the Rx SOH processor 11 by the data processing time by the Tx AU processor 13 and outputting, and a transmission SOH processing portion (Tx SOH processor) 15 for generating and outputting SDH frame data, based on AU data generated by the Tx AU processor 13 and SOH data from the delay processing portion 14.
Thus, SDH data of which data at a desired position of AU portion is substituted with a desired data can be output, for input SDH data, by delaying SOH data detected by the Rx SOH processor 11 by the processing time of AU data by the Rx AU processor 12 and the Tx AU processor 13.
However, as mentioned above, in the method of delaying the processing for SOH data, the circuit scale of the delay processing portion 14 increases extremely and inconveniently.
Especially, for the multi-channeled SDH data, the number of delay phase increases and its circuit scale increases extremely as much.
In other words, SOH data of the number of channels is output at a high speed from the Rx SOH processor 11 to the delay processing portion 14.
On the other hand, the Rx AU processor 12 processes AU data of a particular channel.
This is because, during this processing, the delay processing portion 14 must delay and output a quantity of SOH data.